In integrated circuits having multiple power supplies, as signals cross from one power-supply domain to another, the signals need to be level-shifted. Level shifters can be categorized into two types: high-speed and low-power. Depending on the application of the signal being level-shifted, the application may need a fast data path signal or a slower control signal with lower performance requirements. High-speed level shifters typically require more power and/or greater area than low-power level shifters. Some conventional high-speed level shifters consume both static DC power and transient power associated with switching, while low-power level shifters do not consume static DC power. The transient switching power of both level-shifter types is associated with charging and discharging, as signal potentials change from high to low or low to high.
A low-power level shifter transiently flows current while turning some devices on and other devices off. The transient current is used for the charging and discharging of signal potentials from one rail to another. Low-power level shifter nodes fully swing. The advantage of low-power level shifters is the absence of a static power component; the disadvantage is the relatively low speed. The NFETs of a low-power level shifter are used to over drive the current state of the latch. The larger the NFETs, the faster the transition and the faster the level shifter.
A high-speed level shifter may have nodes that do not swing from rail to rail. In this case, there is DC power for as long as one or more signals are not at a rail voltage. This power is due to a static current passing through an impedance. When current flows, the device is on. As long as current stays flowing, the device stays on. Therefore, the high-speed level shifter has states where some devices flow static current. The advantage is relatively high speed; the disadvantage is relatively high power (both static and transient power components). A high-speed level shifter can be thought of as a current source with an enable/disable.
FIG. 1 shows a schematic diagram of a conventional high-speed level shifter 100 of the prior art. High-speed level shifter 100 converts input signal 102 in the domain of power supply Pwr1 into output signal 104 in the domain of power supply Pwr2. As shown in FIG. 1, p-type field effect transistor (PFET) HP1 is diode-connected, and PFETs HP1 and HP2 are configured to provide a current-mirror scheme. Turning on n-type FET (NFET) HN1 creates a current source between Pwr2 and ground, through HP1 and HN1. This current is mirrored to device HP2.
If input signal 102 is driven towards ground (i.e., low), then inverter 106 drives inverted input signal 108 towards power supply Pwr1. These two signals turn NFET HN1 off and NFET HN2 on, respectively. Turning off HN1 disables the current source, and turning on HN2 drives output signal 104 towards ground. With HN1 off, node 110 will be driven high through the PFET HP1 diode. The HP1 diode will pull node 110 all the way to Pwr2.
If input signal 102 is driven towards power supply Pwr1 (i.e., high in the Pwr1 domain), then HN1 turns on and HN2 turns off, due to inverter 106. Turning on HN1 turns on the current source through HP1/HN1 and drives node 110 low. But node 110 does not go all the way to ground, because of the IR drop across HN1. HN1 has an intrinsic impedance. As the current flows through HN1/HN2, there is a voltage potential created across HN1. This potential is a function of ohms law (V=IR). The current through the HP1 and HN1 devices is mirrored to HP2. With the gate-source voltage being the same across both HP1 and HP2, HP2 turns on. Turning on HP2 drives output signal 104 towards power supply Pwr2 (i.e., high in the Pwr2 domain), thereby converting input signal 102 at Pwr1 into output signal 104 at Pwr2.
Since, as described above, diode-connected HP1 prevents node 110 from swinging from rail to rail (i.e., from ground to Pwr2, and vice versa), level shifter 100 can react quicker to changes in input signal 102 than if node 110 did swing rail to rail.
As described, if input signal 102 is low, then HN1 is off, HN2 is on, and HP1 and HP2 are off. As such, with input signal 102 low, there are no DC paths from power supply Pwr2 to ground. However, if input signal 102 is high, then both HN1 and HP1 are on, and DC current flows through those two transistors from power supply Pwr2 to ground, as represented in FIG. 1. As a result, there is a DC current flowing through high-speed level shifter 100 if input signal 102 is high.
FIG. 2 shows a schematic diagram of a conventional low-power level shifter 200 of the prior art. Like high-speed level shifter 100 of FIG. 1, low-power level shifter 200 converts input signal 202 in the domain of power supply Pwr1 into output signal 204 in the domain of power supply Pwr2. Unlike high-speed level shifter 100 of FIG. 1, which has diode-connected HP1, low-power level shifter 200 has PFETs LP1 and LP2 cross-coupled to provide a latching scheme.
If input signal 202 is driven towards ground (i.e., low), then inverter 206 drives inverted input signal 208 towards power supply Pwr1. These two signals turn NFET LN1 off and NFET LN2 on, respectively. Turning on LN2 drives output signal 204 towards ground, which, in turn, turns on PFET LP1. With LN1 off and LP1 on, LP1 will drive node 210 high, thereby turning off PFET LP2.
If input signal 202 is driven towards power supply Pwr1 (i.e., high in the Pwr1 domain), then LN1 turns on and LN2 turns off, due to inverter 206. Turning on LN1 drives node 210 low, which turns on LP2. Turning on LP2 drives output signal 204 towards power supply Pwr2 (i.e., high in the Pwr2 domain), thereby converting input signal 202 at Pwr1 into output signal 204 at Pwr2. Driving output signal 204 high also turns PFET LP1 off.
As described, if input signal 202 is low, then LN1 is off, LN2 is on, LP1 is on, and LP2 is off. As such, with input signal 202 low, there are no DC paths from power supply Pwr2 to ground. Similarly, if input signal 202 is high, then LN1 is on, LN2 is off, LP1 is off, and LP2 is on. As such, with input signal 202 low, there are also no DC paths from power supply Pwr2 to ground. As a result, there is never a DC current flowing through low-power level shifter 200. On the other hand, low-power level shifter 200 is slower than a comparable implementation of high-speed level shifter 100 due to the time required to flip the latch formed by the cross-coupled PFETs. Typical implementations of low-power level shifter 200 use relatively large NFETs to over-drive the cross-coupled PFETs.